The last bit of the control byte defines the operation tobe performed

　　When set to a one a read operation isselected, and when set to a zero a write operation isselected. The next two bytes received define theaddress of the first data byte (Figure 3-3). Because only A12...A0 are used, the upper three address bitsare don’t care bits.

　　The upper address bits are trans-ferred first, followed by the less significant bits. Following the START condition, the 24XX64 monitorsthe SDA bus checking the device type identifier beingtransmitted.

　　Upon receiving a 1010 code and appropri-ate device select bits, the slave device outputs anAcknowledge signal on the SDA line.

　　Depending on thestate of the R/W bit, the 24XX64 will select a read orwrite operation.FIGURE 3-2: CONTROL BYTE FORMAT3.7 Contiguous Addressing Across Multiple DevicesThe chip select bits A2, A1, A0 can be used to expandthe contiguous address space for up to 512K bits byadding up to eight 24XX64's on the same bus.

　　In thiscase, software can use A0 of the control byte asaddress bit A13, A1 as address bit A14, and A2 asaddress bit A15. It is not possible to sequentially readacross device boundaries.

　　Following the START condition from the master, thecontrol code (four bits), the chip select (three bits), andthe R/W bit (which is a logic low) are clocked onto thebus by the master transmitter. This indicates to theaddressed slave receiver that the address high byte willfollow after it has generated an Acknowledge bit duringthe ninth clock cycle.

　　Therefore, the next byte transmit-ted by the master is the high-order byte of the wordaddress and will be written into the address pointer ofthe 24XX64.

　　The next byte is the Least SignificantAddress Byte. After receiving another Acknowledgesignal from the 24XX64 the master device will transmitthe data word to be written into the addressed memorylocation. The 24XX64 acknowledges again and themaster generates a STOP condition.